Implementing a 50:50 Theory and Lab Pedagogical Model for Verilog HDL: An Outcome-Based Approach

Abstract

The 50:50 Theory-Lab Teaching Model is a successful model for providing Verilog hardware description language (HDL) course material to undergraduate engineering students, with a balanced approach to delivery through both theory (classroom) and lab (practical) experience. The model allows equal opportunities for students to gain both knowledge (theoretical) and hands-on experience (practical). The educational approach used by this model was tested with a group of sixty (60) undergraduate engineering students. The educational techniques associated with this model used the same tools used in the industry ( ModelSim, Xilinx ISE, and Vivado), which were evaluated using a rubric that was later expressed as quantitative data. Statistical methods performed on this quantitative data revealed that the students in the 50:50 Theory-Lab Teaching Model performed more accurately when simulating their designs, were more efficient when debugging their designs, and had a greater understanding of the concepts related to the implementation of Verilog HDL compared to students taught through traditional lecture methods (p < 0.05) with large effect sizes (Cohen's d > 0.80). Therefore, the educational approach developed in this project is a cost-effective and flexible way of delivering course content, thereby enabling students to develop technical competencies and analytical skills and demonstrate job readiness, which meets the objectives of the OBE Principles and NEP 2020 Guidelines. Compared to the baseline, the inputs to this model resulted in an increase of +22%, +24%, and +22% for simulation accuracy, debugging performance, and project evaluation scores, respectively (p-value < 0.01, Cohen’s d > 0.90). Furthermore, SPI improvements, 18.4%, SES efficiencies of 27%, and 21 Concept Retention Gain (CRG) support these findings.