Collaboration of UG-PG Learners for Enhancement of Digital Design Verification Aptitude Using PBL Methodology

Authors

  • Sachin Magdum Department of Electronics and Telecommunication Engineering, RIT, Islampur, Maharashtra
  • Randhir Patil Department of Electronics and Telecommunication Engineering, RIT, Islampur, Maharashtra

DOI:

https://doi.org/10.16920/jeet/2019/v33i1/149022

Keywords:

PBL, Verification Plan, Attainment, VLSI Verification, Collaboration, UG-PG, DSP.

Abstract

The courses like system Verilog, VLSI Design Verification & Testing and Digital Signal Processing are considered for this activity. Delivery of these courses is centralized upon development of verification environment to identify and fix the bugs in DUT (Design Under Test). This is achieved by generating test vectors through programming. The proposed work binds three levels of leaners namely UG, PG and course owner by attaining proficiency in verification of digital design. The methodology is implemented in three major phases namely design of modules, preparation of verification plan and development of verification environment and coverage analysis. Project based learning (PBL) is used to implement the proposed methodology. PBL improved student’s attainment by 15% as compared to previous year in VLSI Verification course. The average marks attained by both UG-PG is 79%.This also helped students to grab placement opportunities in VLSI verification domain. Also students experienced the industry culture of various teams working on single project.

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Published

2019-11-30

How to Cite

Magdum, S., & Patil, R. (2019). Collaboration of UG-PG Learners for Enhancement of Digital Design Verification Aptitude Using PBL Methodology. Journal of Engineering Education Transformations, 107–114. https://doi.org/10.16920/jeet/2019/v33i1/149022

Issue

Volume 33, Special Issue 1, November 2019

Section

Articles
Crossref
Scopus
Google Scholar
Europe PMC

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