D. J., Chaithanya; M., Suchitra; V., Jaswanth; RAIKAR, Amit; SRIVIDYA, Putty; VIJAYA BHASKAR, Seelam Ch. Implementing a 50:50 Theory and Lab Pedagogical Model for Verilog HDL: An Outcome-Based Approach. Journal of Engineering Education Transformations, [S. l.], v. 39, n. Special Issue 2, p. 68–76, 2026. DOI: 10.16920/jeet/2026/v39is2/26009. Disponível em: https://journaleet.in/index.php/jeet/article/view/3541. Acesso em: 20 feb. 2026.